Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - altera sdram

Search list

[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437055 | Author: kevin | Hits:

[Other resource] AlteraSDRAMControllerWhitePaper

Description: Altera SDRAM Controller 白皮书，很详细的文档-Altera SDRAM Controller White Paper, a very detailed document
Platform: | Size: 702000 | Author: wood | Hits:

[Other resource] leon3-altera-ep2s60-sdr

Description: ahb sdram interface.arm cpu series,include controller
Platform: | Size: 98080 | Author: lhxmodelsim | Hits:

[Embeded-SCM Develop] SDRAM

Description: SDRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board
Platform: | Size: 1572577 | Author: 李大同 | Hits:

[Other resource] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114780 | Author: king.xia | Hits:

[Other resource] SDRAM

Description: ALTERA SDR AM Controller White Paper
Platform: | Size: 658903 | Author: 付茗 | Hits:

[Other] sdram

Description: sopc中一个关于sdram的实验，用altera的开发板。-about sdram of sopc
Platform: | Size: 12766208 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] UP_IP_Library_80

Description: altera大学IP库，包含ps2、sdram、rs232等-altera University, IP libraries, including the ps2, sdram, rs232, etc.
Platform: | Size: 5476352 | Author: wcm | Hits:

[VHDL-FPGA-Verilog] CPU11111

Description: altera提供的sdram ip核例程，简单易懂。采用burst8模式。 -altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
Platform: | Size: 1024 | Author: 张寒枫 | Hits:

[Other] ddr_ddr2_sdram9.0

Description: altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
Platform: | Size: 912384 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] sdram-source

Description: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Platform: | Size: 717824 | Author: wela | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] sdr-sdram-(verilog)

Description: Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
Platform: | Size: 777216 | Author: 左左 | Hits:

[VHDL-FPGA-Verilog] SDRAM_ipcore_

Description: Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
Platform: | Size: 1664000 | Author: fangyuanyong | Hits:

[VHDL-FPGA-Verilog] test_sdram

Description: 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block, logic block read SDRAM, SDRAM modules package to read and write, read and write buffer FIFO module, serial module occurs. Altera-based engineering design of the Quartus II 10.1, the software can be used later.
Platform: | Size: 3128320 | Author: | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 用FPGA实现对sdram读写的源代码，芯片用的是Altera公司的，需要的同学可以看看！-FPGA realization of sdram read and write the source code, the chip using Altera' s, students need to take a look!
Platform: | Size: 521216 | Author: zhachshen | Hits:

[VHDL-FPGA-Verilog] vhdl_sdram

Description: Altera Sdram vhdl 控制代码-Altera Sdram vhdl control code
Platform: | Size: 11264 | Author: zhanshen | Hits:

[VHDL-FPGA-Verilog] SDRAM-design-FPGA-altera

Description: SDRAM design FPGA altera-SDRAM design FPGA altera.
Platform: | Size: 719872 | Author: zhaochao | Hits:

[Software Engineering] alter sdr sdram

Description: ALTERA SDR SDRAM controller 说明文档(Altera SDR SDRAM Controller pdf)
Platform: | Size: 702464 | Author: fsc | Hits:
« 1 23 4 5 »

CodeBus www.codebus.net